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open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
GNU Affero General Public License v3.0
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some questions about "phase_offset" in module sync_short #82

Open wwy9931154 opened 1 year ago

wwy9931154 commented 1 year ago

hello sir, thank you for your amazing work.I would like to ask you some tips about the module “sync_short”. There is a output named “phase_offset”,Is this the frequency offset you calculated using a short training sequence(coarse estimation)? I read the comment and found that it seems to be approximated as an integer, what is its range? If I can understand this information, it will definitely be very helpful for my learning. Looking forward to your reply!

JiaoXianjun commented 1 year ago

Yes it is frequency offset. Here you can find how we convert that phase_offset to real frequency offset: https://github.com/open-sdr/openwifi/blob/0dc81d985e5862bcd08b56b692b53312fb4fce95/user_space/side_ch_ctl_src/side_info_display.py#L84

wwy9931154 commented 1 year ago

Thank you very much for your Python code！I am still understanding this code, it is a bit complicated to me. In fact, I am most concerned about the format and range of this Frequency Office in Verilog.I now think it is an integer. Did I understand it right? I saw you in the comment as an example of -8. May I wouder the largest and the smallest range of it? Of course, I will work hard to learn the code you provide, thank you very much for your help！