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open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
GNU Affero General Public License v3.0
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Questions about tx_intf #99

Closed jonasxia closed 5 months ago

jonasxia commented 8 months ago

Hello Jiao,

I'm a doctoral student in the field of communication, and I've recently been studying the FPGA implementation of 802.11. I've been greatly inspired by your OpenWiFi project. I have a question that I haven't been able to fully understand while working on the baseband transmitter.

In the case of dual-stream mode with a 20 MHz bandwidth, I noticed that your project uses a 40 MHz clock for the DAC and a fixed 100 MHz baseband clock. According to your tx_intf module calculations, the 64-bit dac_data is constructed by concatenating two 32-bit outputs from the FIFO. My concern is that, with this calculation, it seems to fall short of achieving a 20 Mbps bandwidth. If you write data at 100 MHz for two beats (the first beat for writing data, and the second for writing all zeros), and then read the data with a 40 MHz clock, the data is delayed by two beats before it is concatenated. As a result, only 10 Mbps bandwidth is achieved. I am also curious about how the 40 MHz bandwidth mode is implemented, and I haven't found a solution for it yet. fifo_re fifo_we

I kindly request your guidance and would greatly appreciate any insights you can provide.

Best regards, Jonas

JiaoXianjun commented 8 months ago

How to calculate the result of "write data at 100 MHz for two beats (the first beat for writing data, and the second for writing all zeros), and then read the data with a 40 MHz clock, the data is delayed by two beats before it is concatenated. As a result, only 10 Mbps bandwidth is achieved."?