CSI real and image part

[hitanvil]

I am reading openwifi's code and seems the real/image part definition in verilog and python parser are different.

1. line 199 of https://github.com/open-sdr/openofdm/blob/064bbe4250672c1237ad053d1a1c54113c30de75/verilog/equalizer.v is

   assign csi = {lts_i_out, lts_q_out};`

   so csi[31:16] is real part, csi[15:0] is image part

2. line 95 of https://github.com/open-sdr/openwifi/blob/master/user_space/side_ch_ctl_src/side_info_display.py is

       tmp_vec_i = side_info[i,8:(num_int16_per_trans-1):4]
       tmp_vec_q = side_info[i,9:(num_int16_per_trans-1):4]
       tmp_vec = tmp_vec_i + tmp_vec_q*1j

   So it uses the low 16-bit as real part a high 16-bit as image part.

Then the two definition are not the same.

[JiaoXianjun]

Thanks for reporting this issue. Indeed it is wrong possibly (I need to double confirm). It looks like another similar issue (iq capture) found in one of our master thesis work: https://users.ugent.be/~xjiao/Jasper_Devreker_masterproef.pdf

His fix is here (in iq_capture.py): https://github.com/redfast00/openwifi/commit/c40b25b4cc39e5172ac013279d9ccbd143b105f8#diff-2353bf6046fda5faba250a27ff768494a82d513e879018538ebd05c2eb8b8dcbL116

We will mark and try to fix.

Or do you already have solution for this?

Would you please tell us how did you find this? (By test? Or just code inspection?)

Thanks!