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open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
GNU Affero General Public License v3.0
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IQ capture cannot receive data #362

Closed Aniwer closed 7 months ago

Aniwer commented 7 months ago

Hardware：Xilinx zedboard + FMCOMMS3 Steps：

  1. The board and PC are in the same LAN. The board IP is 10.10.88.122 and the PC IP is 10.10.88.157. Ping is OK.
  2. Modify Server address in side_ch_ctl.c server.sin_addr.s_addr = inet_addr("192.168.10.1") to server.sin_addr.s_addr = inet_addr("10.10.88.157")，and recompile
  3. Follow the quick start command in iq.md，except insmod side_ch.ko iq_len_init=4095
  4. loop xxx side count info xxx normally display
  5. Modify the UDP _IP in the python script to 10.10.88.157 Results： sock.recvfrom stuck，No txt saving and picture display Is there something wrong with my configuration? Does the loop display normal mean that the board is sending data normally, but the PC is not receiving it normally?
JiaoXianjun commented 7 months ago

Do you have issue with all IPs unchanged?

Aniwer commented 7 months ago

It’s my fault that I didn’t check the startup of the UDP port.

chenmo234 commented 1 month ago

Hello, sorry to bother you. May I ask you some questions regarding IQ capture in OpenWiFi? Here is my contact information: c2385405729.