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open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
GNU Affero General Public License v3.0
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tx_intf module #81

Closed Shangjie-Yang closed 3 years ago

Shangjie-Yang commented 3 years ago

Hello, I notice that in tx_intf module has two data entry ports, s00_axis_tdata[63:0] and dma_data[63:0], If my understanding is correct, the data from s00_axis_tdata[63:0] send into queue by the queuing rules(linux prio) and then run into acc(openofdm), do ofdm modulate, finally the data from acc[31:0] and dma_data[63:0] do once mux,decide who run into dac_intf. so what is the difference between the data stored in s00_axis_tdata[63:0] and dma_data[63:0]？

Thanks

JiaoXianjun commented 3 years ago

dma_data is from the original existing axi_ad9361_dac_dma in the original ADI reference design. It is useless for openwifi. We just keep the original connections for doing nothing.

Shangjie-Yang commented 3 years ago

Thank you for your reply, whether the mux control signal from slv_reg7, also write nothing?

JiaoXianjun commented 3 years ago

we keep the option to connect ad9361 to original axi_ad9361_dac_dma. you can check what we set in the driver of tx_intf. tx_intf.c: TX_INTF_REG_MISC_SEL_write, and figure out.

Shangjie-Yang commented 3 years ago

sure, thanks for your answer.

JiaoXianjun commented 3 years ago

Do you still have other questions?