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Demo projects for various Kintex FPGA boards
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[yosys 0.18 : 0.36][openXC7 0.7.0] cannot place LUTRAM primitives #6

Open hansemro opened 7 months ago

hansemro commented 7 months ago

openXC7 0.7.0 update (more specifically yosys) introduces a build regression for litex-ddr-kc705 and litex-ddr-hpcstore-k420t demos due to unsupported inference of RAM128X1S/RAM256X1S (LUTRAM/Distributed RAM) primitives.

Info: Device utilisation:
Info:             SLICE_LUTX: 12586/407600     3%
Info:              SLICE_FFX:  6139/407600     1%
Info:                 CARRY4:   369/50950     0%
Info:             PSEUDO_GND:     1/86505     0%
Info:             PSEUDO_VCC:     1/86505     0%
Info:                  HARD0:     0/ 3660     0%
Info:               RAMB18E1:     8/  890     0%
Info:               FIFO18E1:     0/  445     0%
Info:           RAMBFIFO36E1:     0/  445     0%
Info:               RAMB36E1:    11/  445     2%
Info:                DSP48E1:     4/  840     0%
Info:                    PAD:   131/ 1460     8%
Info:          IOB33M_OUTBUF:     0/  168     0%
Info:          IOB33S_OUTBUF:     0/  168     0%
Info:           IOB33_OUTBUF:     5/  350     1%
Info:        IOB33M_INBUF_EN:     0/  168     0%
Info:        IOB33S_INBUF_EN:     0/  168     0%
Info:         IOB33_INBUF_EN:     3/  350     0%
Info:   IOB33M_TERM_OVERRIDE:     0/  168     0%
Info:   IOB33S_TERM_OVERRIDE:     0/  168     0%
Info:    IOB33_TERM_OVERRIDE:     0/  350     0%
Info:          PULL_OR_KEEP1:     0/  980     0%
Info:               IDELAYE2:    64/  500    12%
Info:           OLOGICE3_TFF:     0/  350     0%
Info:         OLOGICE3_OUTFF:     0/  350     0%
Info:          OLOGICE3_MISR:     0/  350     0%
Info:              OSERDESE2:   107/  500    21%
Info:           ILOGICE3_IFF:     0/  350     0%
Info:   ILOGICE3_ZHOLD_DELAY:     0/  350     0%
Info:              ISERDESE2:    64/  500    12%
Info:                  BUFIO:     0/   40     0%
Info:             IDELAYCTRL:     3/   10    30%
Info:               BUFGCTRL:     4/   32    12%
Info:                  BSCAN:     0/    4     0%
Info:                   BUFG:     0/   32     0%
Info:               DCIRESET:     0/    1     0%
Info:               DNA_PORT:     0/    1     0%
Info:              EFUSE_USR:     0/    1     0%
Info:              FRAME_ECC:     0/    1     0%
Info:                   ICAP:     0/    2     0%
Info:               INVERTER:     9/  240     3%
Info:    IOB18M_OUTBUF_DCIEN:     9/   72    12%
Info:      IOB18_INBUF_DCIEN:    65/  150    43%
Info:     IOB18_OUTBUF_DCIEN:   102/  150    68%
Info:             MMCME2_ADV:     0/   10     0%
Info:               ODELAYE2:   107/  150    71%
Info:           OLOGICE2_TFF:     0/  500     0%
Info:         OLOGICE2_OUTFF:     0/  500     0%
Info:              PLLE2_ADV:     1/   10    10%
Info:              SELMUX2_1:     4/154550     0%
Info:                STARTUP:     0/    1     0%
Info:             USR_ACCESS:     0/    1     0%
Info:                 BUFHCE:     0/  168     0%
Info:                 BUFFER:     0/  480     0%
Info:           ILOGICE2_IFF:     0/  500     0%
Info:          OLOGICE2_MISR:     0/  500     0%
Info:    IOB18_TERM_OVERRIDE:     0/  150     0%
Info:     IOB18S_INBUF_DCIEN:     0/   72     0%
Info:    IOB18S_OUTBUF_DCIEN:     9/   72    12%
Info:   IOB18S_TERM_OVERRIDE:     0/   72     0%
Info:     IOB18M_INBUF_DCIEN:     9/   72    12%
Info:   IOB18M_TERM_OVERRIDE:     0/   72     0%
Info:     IDELAYE2_FINEDELAY:     0/  150     0%

Info: Placed 687 cells based on constraints.
ERROR: Unable to place cell 'data_mem_grain0.0.0.genblk1.genblk1[0].genblk1.slice', no Bels remaining of type 'RAM128X1S'
0 warnings, 1 error
make: *** [../openXC7.mk:40: xilinx_kc705.fasm] Error 255

Looks like the openXC7 0.7.0 release includes an update to yosys 0.36 (from 0.17), which introduces memory_libmap pass (from 0.18 release). Reverting https://github.com/YosysHQ/yosys/commit/3b2f95953c8b8343f2696c5f47bfb2864417a8b1 stops yosys from inferring unsupported LUTRAM primitives.

hansfbaier commented 7 months ago

Oh, so that issue only shows up for those Kintex parts. Do smaller kintex parts work? I really need to set up a CI. The obvious workaround is using yosys 0.17.

hansemro commented 7 months ago

Oh, so that issue only shows up for those Kintex parts. Do smaller kintex parts work?

Yes, only for kc705 and hpcstore/sitlinv-k420t. Other parts work including qmtech-xc7k325t.

Comparing xilinx_kc705.py and qmtech-xc7k325t.py litex targets, I found that the main difference comes down to the use of PHYPadsReducer. After updating xilinx_kc705 to use [0,1] modules (and no larger subset), yosys no longer infers unsupported LUTRAM primitives.

         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             from litedram.common import PHYPadsReducer
-            self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+            self.ddrphy = s7ddrphy.K7DDRPHY(
+                #PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
+                PHYPadsReducer(platform.request("ddram"), [0, 1]),
                 memtype      = "DDR3",
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
                 module        = MT8JTF12864(sys_clk_freq, "1:4"),
                 l2_cache_size = kwargs.get("l2_size", 8192)

The obvious workaround is using yosys 0.17.

Yes, this much is clear. However, I am interested in getting more primitives supported. Do you mind opening issues tab for prjxray or prjxray-db forks for tracking unsupported primitives?