If N polarity pin is used as single clock BUFG, nextpnr gives error ERROR: Invalid global constant node 'INT_L_X0Y109/VCC_WIRE'

openXC7 / nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices

ISC License

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Open mirekez opened 2 months ago

mirekez commented 2 months ago

Vivado gives error: [DRC PLIO-9] Placement Constraints Check for IO constraints: A clock source clock has been LOCed to a N-Type CCIO :