Closed suarezvictor closed 1 year ago
I receive this issue when using ODDR
ERROR: Failed to route arc 0 of net '$abc$10147$iopadmap$vga_r[0]', from SITEWIRE/OLOGIC_X0Y78/OUTFF_Q to SITEWIRE/IOB_X0Y78/OUSED_OUT.
When using SDR it works, but also with previous version of nextpnr-xilinx (generating the image below) Vivado produces no issue.
Verilog code: https://gist.github.com/suarezvictor/ded5ce54e8533a6f2bf45d555113c114
You need to regenerate the chipdb with the new toolchain version. The old chipdb contains the wrong output wire name SITEWIRE/OLOGIC_X0Y78/OUTFF_OQ instead of SITEWIRE/OLOGIC_X0Y78/OQ
I receive this issue when using ODDR
When using SDR it works, but also with previous version of nextpnr-xilinx (generating the image below) Vivado produces no issue.
Verilog code: https://gist.github.com/suarezvictor/ded5ce54e8533a6f2bf45d555113c114