Thoughts on GTP Module and IBUFDS_GTE2 Primitive

[lgl1227]

I recently came across your work and code contributions related to the Xilinx 7 Series GTP module and the IBUFDS_GTE2 primitive on the nextpnr-xilinx open-source project on GitHub. I am also very interested in FPGA and computer programming, and I am working on similar projects.

While reading Xilinx’s official document UG482_7Series_GTP_Transceivers, I found that the output ports O and ODIV2 of the IBUFDS_GTE2 primitive can be connected not only to the GTREFCLK port of the GPTE2_COMMON but also to BUFG or BUFH.

I instantiated the IBUFDS_GTE2 primitive using Vivado 2020.1 and connected its output to BUFH to create a LED running light effect, and it worked as expected. However, nextpnr-xilinx reports the following error:

ERROR: IBUFDS_GTE2 instance ibufds_gte2_inst output port must be connected to a GTPE2_COMMON instance, but is instead connected to an instance bufh_inst of type BUFH

ug482_7Series_GTP_Transceivers.pdf

module top(
    input wire I,     // 差分时钟输入正
    input wire IB,    // 差分时钟输入负
    input wire rst_n, // 低电平有效的异步复位
    input wire key1,
    output wire [3:0] o_led // 流水灯输出
);

    // 时钟缓冲和分频
    wire clk_buf, clk_buf_bufh, clk;

    IBUFDS_GTE2 ibufds_gte2_inst (
        .O(clk_buf),    // 输出缓冲时钟
        .ODIV2(),       // 分频时钟输出（不使用）
        .CEB(key1),     // 时钟使能（始终使能）
        .I(I),          // 差分时钟输入正
        .IB(IB)         // 差分时钟输入负
    );

    BUFH bufh_inst (
        .O(clk_buf_bufh), // 输出缓冲时钟
        .I(clk_buf)
    );

    // BUFG bufg_inst (
    //     .O(clk),        // 最终时钟输出
    //     .I(clk_buf)
    // );

    // 流水灯逻辑
    reg [31:0] cnt_led;
    reg [3:0]  led;

    always @(posedge clk_buf_bufh or negedge rst_n)
    begin
        if (!rst_n)
        begin
            cnt_led <= 0;
            led <= 4'd1;
        end
        else
        begin
            cnt_led <= cnt_led + 32'd1;

            if ((led == 4'd1) || (led == 4'd2) || (led == 4'd4) || (led == 4'd8))
                led <= cnt_led[25:0] ? led : {led[2:0], led[3]};
            else
                led <= 4'd1;
        end
    end

    assign o_led = ~led; // 输出是LED寄存器的反转值

endmodule

[hansfbaier]

Thanks for reporting this. I am currently on vacation. I will start looking into it in October.

[lgl1227]

Thanks for reporting this. I am currently on vacation. I will start looking into it in October.

OK, I got it. Thank you for your reply. I'll go back and try to solve this problem. If I solve it, I will synchronize the relevant information with you.

[hansfbaier]

If we are lucky it will be quite easy and I can look into it this week.

[lgl1227]

After resolving the error of connecting the IBUFDS_GTE2 output directly to BUFG/BUFH, I found that if the code always @(posedge clk_buf_bufh or negedge rst_n) in top.v contains or negedge rst_n, the generated top.bit file will cause the LED water light to remain in reset when downloaded to the development board. However, if I remove it, the LED water light functions normally. Interestingly, for the top.bit file generated by Vivado, even if top.v contains or negedge rst_n, the top.bit is still valid.