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opencomputeproject / ODSA-BoW

Repo for all activity related to the ODSA Bunch of Wires Specification
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PCIe data rate match #19

Open bapivee opened 4 years ago

bapivee commented 4 years ago

https://github.com/opencomputeproject/ODSA-BoW/blob/009cd9eda3e79b7c0bf5f1e7520417e303ed1640/spec/bow_specification/bow_specification.mdk#L444

Should the spec support specific data rates and striping to match PCIe 1-5 data rates. May also be addressed in the PIPE spec.

mspear79 commented 4 years ago

In my opinion the spec should be flexible as currently described in section 5.1 and not be limited to PCIe data rates. Low latency applications that rely on synchronous or mesochronous clocking between the chips may require specific data rates that are not compatible with PCIe data rates.

For example, a DDR PHY that connects DDR4 3200 MHz DIMMs will require a costly asynchronous buffer and separate clocking infrastructures to transfer to a PCIe-compatible clock frequency.

As discussed earlier, this is okay for 'board to package' applications but not so much for 'chip dis-aggregation' applications.