BoW die-to-die Interface Objectives

[rfarjad]

BoW Objectives (as presented at OCP workshops based on ODSA Industry Surveys)

• A set of backward compatible die-to-die parallel interfaces that provides the flexibility to trade off Throughput/wire, design complexity, cost, packaging technology
• Be inexpensive to implement
• Portable across process nodes ranging from 28nm to at least 5nm
• Portable across multiple bump pitches
• Have the Flexibility to support advanced packaging technology
• Be unencumbered by technology license costs
• Very low power: <1pJ/bit
• Very low latency: <5ns
• Throughput/Chip Edge target range (Rx+Tx):

  100Gbps/mm with all packaging options 1Tbps/mm with preferred packaging option

• Trace length ranges on laminate substrate: Unterminated: <10mm Terminated: <50mm
• Single supply solution supporting a range of Vdds compatible with new process technologies 0.70V – 0.9V
• Target BER of <1E-15 without FEC and with Optional FEC for ultra-low BER < 1E-25

[bapivee]

Changes Ramin's recommending

• A set of backward compatible die-to-die parallel interfaces that provides the flexibility to trade off Throughput/wire, design complexity, cost, packaging technology
• Have the Flexibility to support advanced packaging technology
• Very low power: <1pJ/bit
• Very low latency: <5ns
• Throughput/Chip Edge target range (Rx+Tx): 100Gbps/mm with all packaging options 1Tbps/mm with preferred packaging option
• Single supply solution supporting a range of Vdds compatible with new process technologies 0.70V – 0.9V
• Target BER of <1E-15 without FEC and with Optional FEC for ultra-low BER < 1E-25

[bapivee]

Halil: What is backward compatibility. Needs to be more precisely defined. Bapi: Means any mode defined should be compatible with BoW basic. Halil: How did we get 5 ns. Shahab: Sourced from the memory interface? Carrie: Does the group of statements together imply no AC coupling? Do we want to state that as an objective. Halil: If we use AC coupling area will blow up. John: Fornally preclude AC coupling Halil: Two supplies may be better a choice. 0.7-0.9 may be too high. Bapi: Actual supply value shouldn't be an objective John: Replace actual voltage with a different objective - for example say single vs dual supply or say preferred single supply. The actual value is specified in the spec. Shahab: If you recommend a bump map, recommending two supplies will be hard. Area becomes high. Adoptability can be a challenge Shahab: this is for a chiplet - so specify something more than a conventional ip interface. Carrie: 1E-18 is a common target without FEC. Is there any analysis to back up the claim. Halil: XSR has a 1 e-5 goal. Back up some objective with a line as to why we have it as such.

[bapivee]

A set of backward compatible die-to-die parallel interfaces that provides the flexibility to trade off Throughput/wire, design complexity, cost, packaging technology. Backward as defined by every new mode being compatible with the "Basic mode" defined in this specification. Each future version of this specification is expected to be compatible with at least two previous significant versions.

Be inexpensive to implement.

Portable across process nodes ranging from 28nm to at least 5nm.

Portable across multiple bump pitches.

Have the Flexibility to support advanced packaging technology.

Be unencumbered by technology license costs.

Very low power: <1pJ/bit.

Very low latency: <5ns without FEC, <15 ns with FEC. Latency as defined from the PCS parallel interface at the source, through Tx interface, channel, Rx interface received at the PCS parallel interface at the receiver. Based on experience, the 5 ns target meets the latency requirements of high-performance applications and has been demonstrated to be achievable.

Throughput/Chip Edge target range (Rx+Tx): 100Gbps/mm with all packaging options 1Tbps/mm with preferred packaging option

Trace length ranges on laminate substrate: Unterminated: <10mm Terminated: <50mm

Single supply solution supporting a range of Vdds compatible with new process technologies.

Target BER of <1E-15 without FEC and with Optional FEC for ultra-low BER < 1E-25. Target defined from industry and user feedback. Measure defined to be compatible with the definition for BER for SerDes PHYs.

[bapivee]

Agreed to as objectives by: Carrie, John, Shahab, Halil, Roger, Ramin, MIchael, Bapi

[bapivee]

Text to be added to the spec

---

Target 100 Gbps with all packaging options. As a reference example, be able to achieve this goal at a bump pitch of 130um and with a die edge stack depth no greater than 2 routing layer with organic laminate packaging as a reference example.

Target 1 Tbps/mm with preferred packaging option. As a reference example, be able to achieve this goal with a bump pitch of 50 um and with a die edge stack depth no greater than 4 routing layers with Wafer-Level Fan Out packaging.

Very low power (< 1 pJ/bit) as defined by Tx IO Pad, wire and Rx IO Pad.

---

Other commentary

Need to address < 1 mm.

Should we add a target number that includes the PCS with and without the BER. Potentially budget 30% for de-skewing buffers for higher clock frequencies. The budget for the extras will differ based on the operating mode. Comment from Kenneth based on JEDEC experience for 50mm terminated mode.

We need to bound the packaging complexity for the 1 Tbps/mm target. Without a bounding the complexity of the package, loss compensation, bump pitch i.e. design cost/complexity. Need some commonly accepted definition of packaging complexity - we're calling it routing layers as a placeholder for now.

[bapivee]

What is "preferred" in packaging options. Mean to say "advanced" Specify Bandwidth is unidirectional in targets Change "all packaging options" to "flip chip BGA packaging 150 um bump pitch or finer" Remove reference to "Wafer-Level Fanout" replace with advanced

Won't add the very short reach as an objective. Leave it as an operating mode.

[bapivee]

Final text - at the appropriate locations

Target 100 Gbps with all packaging options. As a reference example, be able to achieve this goal at a bump pitch of 150um and with a die edge stack depth no greater than 2 routing layer with organic laminate packaging as a reference example.

Target 1 Tbps/mm with preferred packaging option. As a reference example, be able to achieve this goal with a bump pitch of 50 um and with a die edge stack depth no greater than 4 routing layers with advanced packaging.

Very low power (< 1 pJ/bit) as defined by Tx IO Pad, wire and Rx IO Pad.

Enable higher throughput at very short reach < 1 mm.

[bapivee]

Agreed to by: Mark, Rita, David, John, Raj, Carrie, Halil, Michael, Shahab, Bapi

[bapivee]

David, John, Mark, Carrie, Halil, Michael, Shahab, Ahmad, Bapi - closed.

[rfarjad]

Please see the attached slides for a proposal for BoW connection between chips. In the meeting I mistakenly mentioned flipped or mirrored version, but the right choice is to only flip 180 degrees to be compatible between chips.

Thanks

On Wed, Dec 11, 2019 at 9:08 AM bapivee notifications@github.com wrote:

David, John, Mark, Carrie, Halil, Michael, Shahab, Ahmad, Bapi - closed.

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[bapivee]

Narrowed inexpensive to include design development and use inexpensive packaging. Issue closed.

[bapivee]

Millind - Should the definition be optimized for laminate? David - Clarify assumptions in bandwidth/mm edge

[bapivee]

Approved 8/20 by Mark, Suresh, Carrie, Greg, Tawfik, Hamid, Shahab, Bapi