Reference bump maps

[bapivee]

Bump pitch in reference bump map examples in the spec and documentation is 130um, Need a note on whether the same maps apply to microbumps with a bump pitch around 50um. Based on a note from Halil.

[bapivee]

Circuit design is not expected to be a limiting factor in shrinking bump pitch. May need to bound and scope any reference bump maps.

Ahmad: Can we say TX/RX signal bump maps be applied to any packaging technology. Can we say it's just the power and ground bumps that may need to change according to the packaging technology. This is consistent with what's in the spec today.

Power delivery for microbumps could be different than for bumps. Need a packaging expert to validate power delivery with wafer-level fanout, interposers.

Need a packaging expert to validate signal routing with interposers/bridges.

Millind: BoW for laminate is a new standard so we can define a new bump map. Should the microbump definition of BoW be a derivative standard that leverages an existing standard such as either AIB or HBM. Then, BoW does not need to define a new bump map. This is not recommending we use AIB or HBM, suggesting that we consider using an existing bump map as a starting reference, Or at least make a case of why we need to define a new reference microbump map.

[bapivee]

Need to produce bump maps for each density and show how they support the preferred bump ordering.

Rita: Need to have these reference bump maps reviewed by packaging and SI experts for escape routes, signal integrity, number of layers.

How do we show that bump maps can interoperate across process nodes. Base definition is likely doable across all bump pitches. Terminated may be challenged. How much current can the microbumps carry?

Will we only consider only north-south orientation for routing - we need to consider east west. See picture to be uploaded to the Github comments. Trade-off between single IP macro vs routing complexity.

Halil will check to see if reference bump maps can be produced.

No bump map can be at the edge of the chip. Will we/should we specify the clearance. May be a pattern, so doesn't matter.

Will the level-shifter be inside or the outside of the bump map. You cannot bring too many power supplies side by side. Most customers do not want to include a level shifter.

ESD Diodes for bumps will be inside the I/O? Can we share across all I/O - a single ESD clip on. That's an implementation decision - should not be a part of the spec, just spec an ESD level (already in the spec.) Leave room for ESD to be outside the bump map.

[bapivee]

Ahmad: Bump maps should be with respect to the chip edge. Ahmad: Flipping and turn 180 bump maps should be a part of the spec. Ramin: Not turning the bump map to the chip edge, makes the routing impractical. Should consider only north-south routing. David/Ramin: Could be possible if the slice is square and the higher router layers change. Ramin: Customers opting to their own PCS. 16 may be too large. Ahmad: will that be a standard. Ahmad: Pin relabeling should be a part of the PHY

[bapivee]

Assumptions for the study:

1. One external power supply. Specification dictates signal ordering, but reference bump map shows power and ground as well.
2. Look at chip-edge oriented bump map (we assume two separate maps for north-south and east-west). So look at near-neighbor straight line or near-neighbor rotated by 90
3. Routing between a bump map and its mirrored version, or a between a bump map and itself on the other part.
4. Study for two bump pitches 55 and 130.
5. Finally look at routing between 55 and 130u bump pitches.