BOM and schematic errata

[wisxxx]

BOM

• item 41 (DS3231 RTC) shows "U5" as ref des. schematic shows "U3A"

• item 40 (1x3 header) does not have corresponding jumpers

• item 29 (IC REG BUCK ADJUSTABLE 2A 8SOIC). Data sheet says this part is not recommended for new designs (add 210817)

• no BOM item for CSAC and SA.3x/SA.5x

• no BOM item for U11 (sch. p.6,A2; assume SiT5721)

• no BOM item for U13 (sch. p.6,B4; assume SiT5356)

• no BOM item for U4 (sch. p.5,C5; BMP388. Note: this part is not recommended for new designs)

• no BOM item for U7 (sch. p.5,D5; AT24MAC402-STUM-T)

SCHEMATIC

• p. 6,C2

  MAC devices SA.3x and SA.5x are labeled "RV-3049-C3"

  Need notation: "Install one of CSAC, SA.3x, or SA.5x".

  Assuming connector U10B would interfere with installation of the CSAC or SA.3x oscillators, need notation: "Install U10B (connector) only if using SA.5x oscillator."

The nets MAC_10Mout, MAC_10Mout, MAC_RF_OUT, and MAC_FREQ_CTL are all shorted, as are MAC_PPSout and MAC_PPS_OUT+, and MAC_PPSin and MAC_PPSIN0+. This is probably related to the oscillator stuffing options as well.

The output dotting should only be on p. 6 where the oscillators are drawn and not on p. 7 at the connector. There should be a note clarifying the operation under the alternative stuffing options (including R17, the zero ohm resistor to GPS_TP1).

[ahmadexp]

Love it. Thank you so much. I will go through the correction list.

[wisxxx]

It appears the the analog frequency control input to the MAC-SA5x oscillator is connected to a digital I/O pin in the FPGA. Is this intended?

In 'Timingcard_SCHEMATICS_BETA_V1.pdf", p. 6,A3 and p. 7,B4, the MAC_FREQ_CTRL net connects the MAC-SA5x INPUT FREQUENCY CONTROL pin (#1) to the FPGA board CON2-B33.

According to the AC7100B FPGA board schematic ("AC7100B_SDM.pdf"), CON2-B33 is routed to Xilinx pin AA10, which is listed in the XC7A100T pinout ("ug475_7Series_Pkg_Pinout.pdf") as a DQS (multifunction) pin.

I assume that analog frequency control is not enabled in the MAC-SA5x. Whatever, the wiring probably needs an update.

[AlphaBetaPhi]

@wisxxx, this is correct. The analog tuning feature is not used and all tuning is performed through the digital interface.

On the FPGA this pin is not used either, it's a placeholder is for alternative versions should they arise in R&D.

[wisxxx]

Issues addressed in subsequent documents.