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opencomputeproject / Time-Appliance-Project

Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
MIT License
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FPGA Design Overview Clarifications #39

Closed wisxxx closed 2 years ago

wisxxx commented 2 years ago

Ref: "Time-Card/SOM/FPGA/Readme.pdf", section 2.4

ahmadexp commented 2 years ago

NetTimeLogic provides a Windows based software that allows you to monitor and set the configurations of the cores. This is an easier (since it is visual) alternative to directly changing values in Linux. In our recent driver though we have most of the settings accessible via the sysfs. This method can still be useful in case someone wants to use the time card without the PCIe being connected, such as event time stamper or IRIG-B generator.

wisxxx commented 2 years ago

Understood. Where does the "host PC running Windows" connect to the FPGA? I'm not seeing it on the AC7100 nor the Timing Card schematics.

thschaub commented 2 years ago

In some versions of the timecard we have an UART (or USB-UART connection). However, the pins are always there in the FPGA design or on the SOM connector.

E.g. Page 4:
https://github.com/opencomputeproject/Time-Appliance-Project/blob/master/Time-Card/ECAD/Prototype-V0/Timingcard_PROJECT.pdf

In the FPGA Design this are following pins:

UART1

set_property PACKAGE_PIN P15 [get_ports Uart1TxDat_DatOut] set_property PACKAGE_PIN P16 [get_ports Uart1RxDat_DatIn]

or on SOM Connector P1B: B-71 UART_TXD B-77 UART_RXD

Details about the UART Communication protocol as well as the Windows Tool you can find here: https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/SOM/FPGA/UCM