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opencomputeproject / Time-Appliance-Project

Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
MIT License
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Production Timecard: bad termination on FPGA JTAG with USB #90

Open wisxxx opened 1 year ago

wisxxx commented 1 year ago

Ref. schematic R4006-G0001-03-SC-REV02.pdf

If using the USB interface (FT432, sht. 24), the FPGA JTAG signals are double-terminated by resistors shown at sht. 24, zone B11:

image

and sht. 10, zone J4.

image

by way of the mux'ing shown on sht. 24 "JTAG/SPI_MASTER_SEL".

ahmadexp commented 1 year ago

@julianstj1 did we address this?

julianstj1 commented 1 year ago

This is on the production card, and the USB interface worked when we tested it, but definitely this double termination should not be there. If we ever have another BOM change on there, I will add this on, thanks for the great catch!