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opencomputeproject / Time-Appliance-Project

Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
MIT License
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Production Timecard: mismatch between board and FPGA PCIe lane counts #92

Open wisxxx opened 1 year ago

wisxxx commented 1 year ago

The production board schematic description on sht. 1 says "X4 PCIE TIME CARD", and four lanes are routed between the edge connector and FPGA (schematic and board). However, the production FPGA only uses a single lane. This lane is correctly attached to the TX0 and RX0 pairs in the board design.

It works, no doubt, but there may be missed expectations for new users.

If going to an x4 channel, during FPGA synthesis are the additional pairs guaranteed to go to the pins already connected on the board?

[ from Vivado block diagram ] image

lasselj commented 1 year ago

Hi Wis! Nice speaking with you the other day. I think you are doing great work :-)

For the production card I don't really mind. For the "normal" modular Timecard, I think this is cool. Most servers don't have slots smaller than x4 and it lets people add their own logic if they want and use x4. I.e. I don't think we should chop it.

(We chopped the x4 connector to x1 on this card. I am sending you one when they arrive)

All the best,

Lasse