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openhwgroup / core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
https://docs.openhwgroup.org/projects/core-v-mcu
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Debug unit reports no harts #213

Closed jeremybennett closed 2 years ago

jeremybennett commented 2 years ago

I have tested the latest work with the genesys2 branch (commit 138c298).

The Verilator model builds using make model-lib. However when the model is included in the test harness, the debug unit is now reporting no harts. I built the Verilator test harness (embench-target repository, target directory, jpb-jtag-driver branch)

$ cd target
$ make clean
$ make

I then run the testbench:

$ ./testbench.exe --test-status --test-gprs --test-fprs --test-csrs
Timescale 1ns / 1ns
TOP.core_v_mcu.i_soc_domain.l2_ram_i.bank_sram_pri0_i.u0
TOP.core_v_mcu.i_soc_domain.l2_ram_i.bank_sram_pri1_i.u0
TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[0].bank_i.u0
TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[1].bank_i.u0
TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[2].bank_i.u0
TOP.core_v_mcu.i_soc_domain.l2_ram_i.CUTS[3].bank_i.u0
IDCODE = 0x10001c05 [version = 0x1, part # =  0x0001, manuf ID: 0x602 [JEP106 ID = 0x02, continuation # = 12]]
DTMCS = 0x00001071 [dmihardreset = false, dmireset = false, idle = 1, dmistat = 0, abits = 7, version = 1, addr mask = 0000007f]
Max HARTS: 0x00100000
Testing HART availability

Warning dmiWrite retry requested
Warning dmiRead retry requested
Hart 0, dmstatus: 0x03ffffc1 [ impebreak = true, havereset = true, resumeack = true, nonexistent = true, unavail = true, running = true, halted = true, authenticated = true, authbusy = true, hasresethaltreq = false, confstrptrvalid = false, version = 1 ]

Num harts: 0

The messages about retry requested are worrying, and ISTR we saw the same when we had problems previously.

gmartin102 commented 2 years ago

Issue is fixed by correcting the PLL simulation model. Verilator clock generation is significantly different from soc and emulation clocks and the inclusion of the PLL model failed to source the verilator clocks correctly.

timsaxe commented 2 years ago

Do we need to add something to either CI or regression to catch this earlier?

From: Greg Martin @.> Sent: Tuesday, February 1, 2022 11:01 AM To: openhwgroup/core-v-mcu @.> Cc: Subscribed @.***> Subject: Re: [openhwgroup/core-v-mcu] Debug unit reports no harts (Issue #213)

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Issue is fixed by correcting the PLL simulation model. Verilator clock generation is significantly different from soc and emulation clocks and the inclusion of the PLL model failed to source the verilator clocks correctly.

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MikeOpenHWGroup commented 2 years ago

Hi gang - a few comments on this one:

  1. Please push changes from your local fork to the dev branch of this repo.
  2. We should not merge anything up to the master branch until it has successfully passed regressions in simulation, emulation and Verilator.
  3. Please let the originator of an issue be the one to close it. @jeremybennett is the originator of this issue, so I will reopen it for his comment.
jeremybennett commented 2 years ago

@gmartin102 Thanks for the quick turnaround. Tested and all working sweetly.