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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
https://docs.openhwgroup.org/projects/core-v-mcu
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APB Timer Register Definition #239

Open datum-dpoulin opened 1 year ago

datum-dpoulin commented 1 year ago

The MCU UVM project has begun building Sub-System level test benches. We started with the APB Timer.

We used the spreadsheet included in the MCU source to build a csv file to generate the UVM register model from.

We found that the access policy for the fields does not match reality, for instance CFG_REG_LOW.reset_bit and CFG_REG_HI.reset_bit should be marked as 'W1C' or similar.

There are 2 issues here:

  1. The register definition spreadsheets are not standardized from block to block as far as which columns correspond to what information. In order to use UVM register models and automated testing, we need to standardize so that the model can be automatically generated.
  2. The access policy used in the spreadsheets MUST be from the UVM list.

For #2, here is the list of access policies that are "UVM-legal":

”RO”    W: no effect, R: no effect
”RW”    W: as-is, R: no effect
”RC”    W: no effect, R: clears all bits
”RS”    W: no effect, R: sets all bits
”WRC”   W: as-is, R: clears all bits
”WRS”   W: as-is, R: sets all bits
”WC”    W: clears all bits, R: no effect
”WS”    W: sets all bits, R: no effect
”WSRC”  W: sets all bits, R: clears all bits
”WCRS”  W: clears all bits, R: sets all bits
”W1C”   W: 1/0 clears/no effect on matching bit, R: no effect
”W1S”   W: 1/0 sets/no effect on matching bit, R: no effect
”W1T”   W: 1/0 toggles/no effect on matching bit, R: no effect
”W0C”   W: 1/0 no effect on/clears matching bit, R: no effect
”W0S”   W: 1/0 no effect on/sets matching bit, R: no effect
”W0T”   W: 1/0 no effect on/toggles matching bit, R: no effect
”W1SRC” W: 1/0 sets/no effect on matching bit, R: clears all bits
”W1CRS” W: 1/0 clears/no effect on matching bit, R: sets all bits
”W0SRC” W: 1/0 no effect on/sets matching bit, R: clears all bits
”W0CRS” W: 1/0 no effect on/clears matching bit, R: sets all bits
”WO”    W: as-is, R: error
”WOC”   W: clears all bits, R: error
”WOS”   W: sets all bits, R: error
”W1”    W: first one after HARD reset is as-is, other W have no effects, R: no effect
”WO1”   W: first one after HARD reset is as-is, other W have no effects, R: error
”NOACCESS”  W: no effect, R: no effect
MikeOpenHWGroup commented 1 year ago

Hi @datum-dpoulin, I am not sure that the access behaviour of CORE-V-MCU CSRs needs to conform to "UVM legal access polices". Having said that, I would be surprised if the list you provided is insufficient for our needs so let's start there.

@gmartin102, at fiest glance this appears to be a bug in the CSV register spec. What do you think?