xcvalu carry bit for add+shift operation

openhwgroup / core-v-sw

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Closed realqhc closed 8 months ago

realqhc commented 9 months ago

https://github.com/llvm/llvm-project/pull/78138#discussion_r1452688437 From the spec there is a carry bit as mentioned in comment above, is this true that the bit is retained after shift operation?

pascalgouedo commented 9 months ago

As replied in https://github.com/llvm/llvm-project/pull/78138, there is no carry in RISC-V spec. And same for intermediate computation result.