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openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.
https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html
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. #165

Closed ShashankVM closed 4 years ago

ShashankVM commented 4 years ago

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MikeOpenHWGroup commented 4 years ago

With respect @ShashankVM, your interpretation of the situation is not correct. Solderpad is a permissive open-source license which means that the project(s) licensed under it can use closed-source contributions.

MikeOpenHWGroup commented 4 years ago

I am not a lawyer, but I disagree. We can be dependent on close source code and we can distribute it (e.g. have compiled objects in our public repository).

rickoco commented 4 years ago

Hello @ShashankVM - thanks for your comments, but to be clear, we are not distributing proprietary code and calling it open-source. Our CORE-V Verification Test Bench leverages several commercial, closed source, tools with commercial System Verilog simulators being the most obvious and the Imperas ISS another example. Within the OpenHW environment, we use dsim from Metrics, Xcelium from Cadence for SV simulation and the Imperas ISS to run our open-source test bench. All of the stimulus in the test bench is open-source and available for any user to freely adopt / modify for use with whatever SV simulator or ISS reference model they would like to use.

ShashankVM commented 4 years ago

Western Digital has also created open-source RISC-V cores written in SystemVerilog. Their Instruction Set Simulator is open-source, as it should be. https://github.com/westerndigitalcorporation/swerv-ISS

rickoco commented 4 years ago

@ShashankVM - this will be my last reply on this topic as it is clear we'll need to 'agree to disagree'. The OpenHW Group was established to curate well verified, high quality, open-source IP using the best tools available for the job (commercial or otherwise). The CORE-V Verification Test Bench our community has built follows that strategy. As I posted earlier, all of the stimulus in the test bench is open-source and available for any user to freely adopt / modify for use with whatever SV simulator or ISS reference model they would like to use. The user can disable the automatic inclusion of the Imperas ISS and use whatever ISS they choose.

rickoco commented 4 years ago

Okay @rickoco. I will create a separate fork of this entire project with an open-source ISS (or other open-source technology). My fork will also be licenced under the Solderpad Hardware Licence and I'll make sure it will be vendor-neutral. @MikeOpenHWGroup

Hello @ShashankVM that is exactly what we're expecting will occur as users adopt the CORE-V Verification Test Bench which is how support for VCS and Questa was added beyond the original dsim and Xcelium work. Feel free to stay engaged to keep your work in sync with new capability commits in the test bench and to add back any improvements you make.

ShashankVM commented 4 years ago

Okay @rickoco. I will create a separate fork of this entire project with an open-source ISS (or other open-source technology). My fork will also be licenced under the Solderpad Hardware Licence and I'll make sure it will be vendor-neutral. @MikeOpenHWGroup

Hello @ShashankVM that is exactly what we're expecting will occur as users adopt the CORE-V Verification Test Bench which is how support for VCS and Questa was added beyond the original dsim and Xcelium work. Feel free to stay engaged to keep your work in sync with new capability commits in the test bench and to add back any improvements you make.

Yes, @rickoco. Thank you.