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openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.
https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html
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ISS/TB: Properly enable mnxti/mscratchcsw/mscratcswl-checking with ISS #2088

Open silabs-hfegran opened 1 year ago

silabs-hfegran commented 1 year ago

Task Outcome

Currently mnxti, mscratchcsw and mscratchcswl are marked as volatile, which implies that their value will be copied from the values that the RTL reports. This needs a proper fix, so this task is here to keep this in mind.

Proper fix: The read value of these registers is only valid when there is a valid csr read that accesses these registers. At any other point in time, the value of these "registers" can not be compared. The ISS needs to take this into account, and when that is in place, the volatile-statement in the uvmt_cv32e40<s/x>_imperas_dv_wrap for these registers must be removed.

Location Information

core-v-verif/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dv_wrap.sv core-v-verif/cv32e40s/tb/uvmt/uvmt_cv32e40x_imperas_dv_wrap.sv

Completion Criteria

Registers are no longer marked as volatile in the test bench, and there should be no related mismatches during test-runs that are caused by a failure to properly compare valid values.

silabs-robin commented 11 months ago

I'm not sure if/how this relates to https://github.com/openhwgroup/core-v-verif/issues/2147

silabs-robin commented 11 months ago

Seems this is not fixed yet:

It is still volatile, with a todo, and temporarily commenting that out gives iss mismatch.

bilde