[cv_dv_utils pulse gen] To add pulse generator(new uvm driver) in cv_dv_utils

[khandelwaltanuj]

Hello,

A new uvm driver pulse generator is added in the cv_dv_utils.

Here is a little detail. The Pulse Gererator is a SystemVerilog UVM module which is used to configure and generate pulses. Pulse Generator can be configured to generate multiple pulses. A pulse can be a sysncronous pulse with respect to a clock or an asynchronous pulse. Timeunit of pico second is used to genarate an asynchronous pulse.

The new driver has been tested in the TB of HPDCache, where it is used to generator the signal flush. And we would like to commit it to the open source.

Thanks and regards Tanuj Khandelwal

[MikeOpenHWGroup]

Hi @khandelwaltanuj and thanks for your interest in contributing to CORE-V-VERIF. Please review CONTRIBUTING and make sure you are covered by the Eclipse Contributor Agreement either as an individual or through your Institution. It might also be useful to review the CORE-V-VERIF coding style guidelines.

Please also ensure that all files have the appropriate license header. A good example from cv_dv_utils is here, but you can choose a simple two-liner SPDX header like this:

// Copyright {year} {owner}
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

Note that we readily accept open-source contributions with either an EPL-2.0, Apache-2.0 or Solderpad-2.1 license. Other licenses may be accepted, but will require a longer review.

I am somewhat confused about whether this verification component is a SystemVerilog module or a SystemVerilog class (possibly extended from a class in the UVM library). If it is a module, then it could be placed in lib/cv_dv_utils/sv. If it is a UVM class, then lib/cv_dv_utils/uvm is the appropriate location.

I look forward to your pull-request!

[khandelwaltanuj]

Hi @MikeOpenHWGroup

It is a drived class from uvm_driver. It contains following components

pulse_gen_driver extend uvm_driver (dummy, dummy) --> pulse gen configuration class --> pulse gen interface

I hope you have now a clear picture of it.

Thanks and regards Tanuj Khandelwal

[MikeOpenHWGroup]

Thanks @khandelwaltanuj. As mentioned in #2408, lets move this discussion the TWG:Verification channel on MatterMost and we can discuss it there.

When you are ready to make your contribution, please create a pull-request and be sure to follow the contribution guidelines above.