openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.
https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html
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corev-dv rand test issue #2539

Open vinomutty opened 1 week ago

vinomutty commented 1 week ago

Hi Please find below commands used for running test cases

command lines: Available test programs export CV_SW_MARCH=rv32imc export CV_SW_PREFIX=riscv32-unknown-elf- export CV_SW_TOOLCHAIN=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1 export RISCV=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1

For custom testcase :make test TEST= riscv_arithmetic_basic_test_0 CV_SIMULATOR=vsim USE_ISS=IMPERAS OVPSIM

COREV-DV Generated Tests: make SIMULATOR=vsim corev-dv make gen_corev-dv test TEST=corev_rand_arithmetic_base_test SIMULATOR=vsim USE_ISS=IMPERAS OVP

error.txt

Thanks

MikeOpenHWGroup commented 1 week ago

Hi @vinomutty, this Issue seems to be the same one as #2537. If that is the case, please close that Issue and we will continue the discussion here.

A couple of comments:

You can try a few things:

  1. Make sure you are using the cv32e40p/dev branch of the core-v-verif repo. This is very important.
  2. In the cv32e40p/sim/uvmt directory run make clean_all SIMULATOR=vsim and re-run the test.
  3. Try the CORE-V prebuilt toolchain mentoned in the README (see my comment in #2537).