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openhwgroup / core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en
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exc, excode, dbg and err still present #183

Closed pascalgouedo closed 3 months ago

pascalgouedo commented 3 months ago

Even if this issue #151 is marked as merged and closed with PR #152 those 4 signals are still in v1.0.0-rc.1.

I completely understand that dbg and err should be moved to Memory interface.

But I don't get the point of moving exc/exccode as well. I think any non-memory instruction should be able to report an exception related to its own architectural definition if wanted.

Proposed resolution

Remove dbg and err.

Explain how to signal exceptions to the CPU if exc* are moved to Memory interface.

christian-herber-nxp commented 3 months ago

It was fixed after v1.0.0-rc.1. It will not be in v1.0.0

pascalgouedo commented 3 months ago

What about exc/exccode? Still moved to memory interface? If local XS is off, how to answer with illegal instruction error without memory interface?

christian-herber-nxp commented 3 months ago

By not accepting the instruction. Then nobody will accept it an an illegal instruction trap will happen. But maybe that's a fair point to put into the spec explicitly