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openhwgroup / core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en
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Adding a note to explain the rational for offloading decompressed ins… #196

Closed christian-herber-nxp closed 7 months ago

christian-herber-nxp commented 7 months ago

…tructions preferably to the coprocessor

MPEZZIN commented 7 months ago

That spec item is there simply so that if a coprocessor claims a 16-bit instruction it is also supposed to handle the corresponding 32-bit instruction (no matter what it is). The coprocessor is still free to not accept that 32-bit instruction but that would be weird.

A simple (not so weird) example that comes to my mind is a coprocessor that would handle instruction decompression only. There are people pushing for a modular processor design approach that would rely on CV-X-IF instead of a parametric monolithic design.