search

openhwgroup / core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en
Other
60 stars 24 forks source link

[Review Comment]: Compressed itf only for compressed instructions #201

Closed Silabs-ArjanB closed 7 months ago

Silabs-ArjanB commented 7 months ago

Comment

image

Proposed Resolution

See above

Addition Info

No response

christian-herber-nxp commented 7 months ago

did we not discuss this in one of the meetings and concluded it was not necessary to put such a restriction into the spec?

Silabs-ArjanB commented 7 months ago

I forgot the conclusion and I don't think it matters much, but we need to make either choice explicit (I don't care what choice)

christian-herber-nxp commented 7 months ago

as the coprocessor has to anyway inspect the LSBs, I would put the requirement on the copro. At the same time, the CPU will likely anyway be aware of the instruction length, as it has to obtain 16B from the prefetch buffer. But putting the restriction on the copro is I think the smaller restriction