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openhwgroup / core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en
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[Review Comment]: Register interface underspecified #204

Closed Silabs-ArjanB closed 5 months ago

Silabs-ArjanB commented 6 months ago

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christian-herber-nxp commented 6 months ago

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Ok done

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This Section you are referring to is interesting. I do not think commit has a very concrete place in the instruction flow. In many implementations, it might happen at the same time as result.

I think it should be possible for implementations to chose to have commit earlier than register. Especially as in split scenario, a register transaction is not be initiated if the operand is not available. Then there is time for an exception or so which would result in the transaction being killed, before its operands are provided.

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True. I updated.

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Issue should be the only limitation. If issue happens, but result doesnt for a while, a commit with kill should be possible.

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ok done

christian-herber-nxp commented 6 months ago

additional note: I did also share the interface sequence, so now commit is before register. I do think however, that this section is a bit confusing, as it refers to an instruction flow, and that may clearly be different (e.g. commit after an eventual memory transaction).