Closed Gchauvon closed 1 month ago
I believe there is a typo in the description of the encoding space for rs3 in [31:27] only for R4-type instructions.
rs3
[31:27]
https://github.com/openhwgroup/core-v-xif/blob/bdf5f1c89313dac1cf21160f1b84fa9f43becccf/docs/source/x_ext.rst?plain=1#L259
I propose :
If an offloaded instruction uses the register file source rs3, then these are encoded in instruction bits [31:27] if the instruction uses the major opcodes MADD, MSUB, NMSUB, or NMADD (R4-type).
No response
Comment
I believe there is a typo in the description of the encoding space for
rs3in[31:27]only for R4-type instructions.Proposed Resolution
https://github.com/openhwgroup/core-v-xif/blob/bdf5f1c89313dac1cf21160f1b84fa9f43becccf/docs/source/x_ext.rst?plain=1#L259
I propose :
If an offloaded instruction uses the register file source
rs3, then these are encoded in instruction bits[31:27]if the instruction uses the major opcodes MADD, MSUB, NMSUB, or NMADD (R4-type).Addition Info
No response