Closed MaryBennett closed 10 months ago
Hi @MaryBennett There are no pre-incremented instructions right now, just the post ones.
For per-* ones, I think I made a mistake and to be really ARM-like, a comma should be added after register name in the parenthesis.
Pre-* cv.lw rd, (rs1, +/- imm/rs2)!
Corresponding pull request has been merged
Update instruction names to match documentation.
Corresponding GCC issue: https://github.com/openhwgroup/corev-gcc/issues/60
ARM-like Pre- cv.lw rd, (rs1, +/- imm/rs2)! Post- cv.lw rd, (rs1), +/-imm/rs2