simulator

[rcvlr]

Hello, we're using the cv32e40p on FPGA and building FW for it using the corev-gcc toolchain. We added a custom instruction and I could add it to corev-gcc so we can actually use it (btw, thanks for the great work).

I was now looking for a simulator (doesn't have to be cycle-accurate), and I stumble upon the gdb sim target for risc-v and the one from Imperas. From what I understood so far, the risc-v gdb simulator doesn't support any corev extension, which are on the other hand supported by the Imperas simulator. If I understand correctly, however, to add a custom instruction the Imperas simulator requires to get in touch with Imperas, as the simulator is not open source.

On the simulator landscape is also Spike, which seems to be straightforward to extend with new instructions. I was wondering if there is any reason why the corev extensions are not present in Spike, and what would be in your opinion the best way to add corev and custom extensions to an open source simulator.

[MaryBennett]

We are working on a software solution.

[jeremybennett]

It would be perfectly feasible to extend the GDB simulator, but I know of no one willing to work on this. Similarly it would be possible to add CORE-V to Spike, although I do not know that project's position on accepting vendor extensions upstream.

There is a project started by Wei Wei of ISCAS PLCT to add CORE-V support to QEMU, but this needs someone to pick up the work.

Finally there is a proposal in preparation for OpenHW Group to develop a generic Verilator model for all RISC-V cores, including CV32E40Pv2 with all the extensions. This proposal is expected to be considered by the OpenHW Technical Working Group in July or August.

I'll leave this issue open, but tag as an enhancement.