Add post-increment and reg-reg load/store instructions, and GAS tests

[EnricoTabanelli]

gas/ChangeLog.COREV:

* config/tc-riscv.c (riscv_multi_subset_supports): Add 
post-increment and register-indexed load/store instruction 
class. 
(validate_riscv_insn, riscv_ip): Add post-increment symbol.
* doc/c-riscv.texi: Added details on CORE-V post-incrementing
and reg-reg load/store ops ISA options.

gas/testsuite/ChangeLog.COREV:

* gas/riscv/cv-mem-fail-operand-01.d: Add post-increment
and register-indexed load/store test.
* gas/riscv/cv-mem-fail-operand-01.s: Likewise.
* gas/riscv/cv-mem-fail-operand-01.l: Likewise.
* gas/riscv/cv-mem-fail-operand-02.d: Likewise.
* gas/riscv/cv-mem-fail-operand-02.s: Likewise.
* gas/riscv/cv-mem-fail-operand-02.l: Likewise.
* gas/riscv/cv-mem-fail-operand-03.d: Likewise.
* gas/riscv/cv-mem-fail-operand-03.s: Likewise.
* gas/riscv/cv-mem-fail-operand-03.l: Likewise.
* gas/riscv/cv-mem-fail-operand-04.d: Likewise.
* gas/riscv/cv-mem-fail-operand-04.s: Likewise.
* gas/riscv/cv-mem-fail-operand-04.l: Likewise.
* gas/riscv/cv-mem-fail-operand-05.d: Likewise.
* gas/riscv/cv-mem-fail-operand-05.s: Likewise.
* gas/riscv/cv-mem-fail-operand-05.l: Likewise.
* gas/riscv/cv-mem-fail-march.d: Likewise.
* gas/riscv/cv-mem-fail-march.s: Likewise.
* gas/riscv/cv-mem-fail-march.l: Likewise.
* gas/riscv/cv-mem-lb.d: Likewise.
* gas/riscv/cv-mem-lbpost.d: Likewise.
* gas/riscv/cv-mem-lbpost.s: Likewise.
* gas/riscv/cv-mem-lbrr.d: Likewise.
* gas/riscv/cv-mem-lbrrpost.d: Likewise.
* gas/riscv/cv-mem-lbrrpost.s: Likewise.
* gas/riscv/cv-mem-lbrr.s: Likewise.
* gas/riscv/cv-mem-lb.s: Likewise.
* gas/riscv/cv-mem-lbu.d: Likewise.
* gas/riscv/cv-mem-lbupost.d: Likewise.
* gas/riscv/cv-mem-lbupost.s: Likewise.
* gas/riscv/cv-mem-lburr.d: Likewise.
* gas/riscv/cv-mem-lburrpost.d: Likewise.
* gas/riscv/cv-mem-lburrpost.s: Likewise.
* gas/riscv/cv-mem-lburr.s: Likewise.
* gas/riscv/cv-mem-lbu.s: Likewise.
* gas/riscv/cv-mem-lh.d: Likewise.
* gas/riscv/cv-mem-lhpost.d: Likewise.
* gas/riscv/cv-mem-lhpost.s: Likewise.
* gas/riscv/cv-mem-lhrr.d: Likewise.
* gas/riscv/cv-mem-lhrrpost.d: Likewise.
* gas/riscv/cv-mem-lhrrpost.s: Likewise.
* gas/riscv/cv-mem-lhrr.s: Likewise.
* gas/riscv/cv-mem-lh.s: Likewise.
* gas/riscv/cv-mem-lhu.d: Likewise.
* gas/riscv/cv-mem-lhupost.d: Likewise.
* gas/riscv/cv-mem-lhupost.s: Likewise.
* gas/riscv/cv-mem-lhurr.d: Likewise.
* gas/riscv/cv-mem-lhurrpost.d: Likewise.
* gas/riscv/cv-mem-lhurrpost.s: Likewise.
* gas/riscv/cv-mem-lhurr.s: Likewise.
* gas/riscv/cv-mem-lhu.s: Likewise.
* gas/riscv/cv-mem-lw.d: Likewise.
* gas/riscv/cv-mem-lwpost.d: Likewise.
* gas/riscv/cv-mem-lwpost.s: Likewise.
* gas/riscv/cv-mem-lwrr.d: Likewise.
* gas/riscv/cv-mem-lwrrpost.d: Likewise.
* gas/riscv/cv-mem-lwrrpost.s: Likewise.
* gas/riscv/cv-mem-lwrr.s: Likewise.
* gas/riscv/cv-mem-lw.s: Likewise.
* gas/riscv/cv-mem-march-rv32i-xcorev.d: Likewise.
* gas/riscv/cv-mem-march-rv32i-xcorev.s: Likewise.
* gas/riscv/cv-mem-sb.d: Likewise.
* gas/riscv/cv-mem-sbpost.d: Likewise.
* gas/riscv/cv-mem-sbpost.s: Likewise.
* gas/riscv/cv-mem-sbrr.d: Likewise.
* gas/riscv/cv-mem-sbrrpost.d: Likewise.
* gas/riscv/cv-mem-sbrrpost.s: Likewise.
* gas/riscv/cv-mem-sbrr.s: Likewise.
* gas/riscv/cv-mem-sb.s: Likewise.
* gas/riscv/cv-mem-sh.d: Likewise.
* gas/riscv/cv-mem-shpost.d: Likewise.
* gas/riscv/cv-mem-shpost.s: Likewise.
* gas/riscv/cv-mem-shrr.d: Likewise.
* gas/riscv/cv-mem-shrrpost.d: Likewise.
* gas/riscv/cv-mem-shrrpost.s: Likewise.
* gas/riscv/cv-mem-shrr.s: Likewise.
* gas/riscv/cv-mem-sh.s: Likewise.
* gas/riscv/cv-mem-sw.d: Likewise.
* gas/riscv/cv-mem-swpost.d: Likewise.
* gas/riscv/cv-mem-swpost.s: Likewise.
* gas/riscv/cv-mem-swrr.d: Likewise.
* gas/riscv/cv-mem-swrrpost.d: Likewise.
* gas/riscv/cv-mem-swrrpost.s: Likewise.
* gas/riscv/cv-mem-swrr.s: Likewise.
* gas/riscv/cv-mem-sw.s: Likewise.

include/ChangeLog.COREV:

* riscv-opc.h: Add post-increment and register-indexed 
load/store matches and masks.
* riscv.h (riscv_insn_class): Add post-increment and
register-indexed load/store class.

opcodes/ChangeLog.COREV:

* riscv-dis.c (print_insn_args): Add post-increment symbol. 
* riscv-opc.c (riscv_opcodes): Add post-increment and 
register-indexed load/store opcodes.

Signed-off-by: Enrico Tabanelli enrico.tabanelli@embecosm.com

[jessicamills]

Good to merge. Built branch locally and ran tests:

        === gas Summary ===

# of expected passes        482
# of expected failures      21
# of unsupported tests      5

        === ld Summary ===

# of expected passes        406
# of expected failures      4
# of untested testcases     26
# of unsupported tests      182