Linker does not test HW loop offsets are in range.

[jeremybennett]

Consider the following:

# Test if symbolic arguments to starti work.
#
#   Macro to generate word length NOPS
#
    .macro wnops count=1
    nop
    nop
    .ifne \count
    wnops "(\count-1)"
    .endif
    .endm
#
#   Declare as a global function so it will link
#
    .global main
    .func main
main:
    cv.setupi 0, 42, lp0
    wnops   29
lp0:
    cv.setupi 0, 561, lp1
    wnops   30
lp1:

Compile and link

riscv32-corev-elf-gcc -march=rv32imac_xcorevhwlp1p0 /tmp/1.s -o /tmp/1.o

Note no errors, but objdump shows the second of these, the branch has overflowed:

$ riscv32-corev-elf-objdump -d /tmp/1.o

000101ee <lp0>:
   101ee:       2310462b                cv.setupi       0,561,101ee <lp0>
   101f2:       0001                    nop
   101f4:       0001                    nop
   101f6:       0001                    nop
   ...

[Clay-Cui]

Hi, I tried to use this compiler to compile a piece of c code and generate the asm codes using the hardware loop of cv32e40p. However, no matter how I tried, the compiled asm codes does not utilize the cv.count/start/end instructions, but original bne instruction. In cv32e40p manual, it says the compiler will generate instructions trying to use the hardware loop without needing of asm codes. Is this the right compiler that I'm looking for? Thank you in advance.

[MaryBennett]

The patch https://github.com/openhwgroup/corev-binutils-gdb/commit/ee3f41b4fbcf57bc8985d84cd57ce0171a540faa fixes this issue by moving overflow checking to the linker. A couple of tests have been added too.

[MaryBennett]

Hi, I tried to use this compiler to compile a piece of c code and generate the asm codes using the hardware loop of cv32e40p. However, no matter how I tried, the compiled asm codes does not utilize the cv.count/start/end instructions, but original bne instruction. In cv32e40p manual, it says the compiler will generate instructions trying to use the hardware loop without needing of asm codes. Is this the right compiler that I'm looking for? Thank you in advance.

Currently, CORE-V's GCC cannot yet generate hardware loops. The documentation describes what the compiler will be able to do. We plan to start work on this in a couple of months.

[NandniJamnadas]

@jeremybennett This issue can now be closed.