Post-Increment Register-Immediate Load should be updated

[ChunyuLiao]

https://github.com/openhwgroup/corev-binutils-gdb/blob/development/gas/testsuite/gas/riscv/cv-mem-lb.s cv.lb t0, -2048(t2) cv.lb t4, 15(t1) cv.lb t3, 2047(t5)

these instructions should be updated to: cv.lb t0, -2048(t2!) cv.lb t4, 15(t1!) cv.lb t3, 2047(t5!)

[NandniJamnadas]

This is a mistake in the GNU assembler and in the testing. We have accidentally defined cv.lb rd, imm(rs) as a synonym of standard RISC-V lb. The same appears for all the other CORE-V loads and stores. We will remove this and update the tests.

[NandniJamnadas]

This issue is now fixed with pull request #90 CV32E40Pv2 Update Post Increment Load/Store.