CV32E40Pv2 MAC pseudo-instructions

[NandniJamnadas]

This is where `cv.mul* rD, rs1, rs2` is `cv.mul*n rD, rs1, rs2, 0`.

* include/opcode/riscv-opc.h: Removed corresponding MATCH and MASK macros.
* opcodes/riscv-opc.c: Implemented:
    * MASK_CV_MAC_UIMM5 macro which masks 0 for Is3 operand
    * infrastructure for CORE-V MAC alias instructions.
* gas/testsuite/gas/riscv/cv-mac-mulhhs.d: Updated tests.
* gas/testsuite/gas/riscv/cv-mac-mulhhs.s: Likewise.
* gas/testsuite/gas/riscv/cv-mac-mulhhu.d: Likewise.
* gas/testsuite/gas/riscv/cv-mac-mulhhu.s: Likewise.
* gas/testsuite/gas/riscv/cv-mac-muls.d: Likewise.
* gas/testsuite/gas/riscv/cv-mac-muls.s: Likewise.
* gas/testsuite/gas/riscv/cv-mac-mulu.d: Likewise.
* gas/testsuite/gas/riscv/cv-mac-mulu.s: Likewise.

[NandniJamnadas]

GNU Assembler Results:

| Category             | Previous | Current  | Delta   |
| :------------------- | -------: | -------: | -------:|
| Expected passes      |     1256 |     1256 |       - |
| Unexpected failures  |        - |        - |       - |
| Unexpected successes |        - |        - |       - |
| Expected failures    |       25 |       25 |       - |
| Unresolved testcases |        - |        - |       - |
| Unsupported tests    |        9 |        9 |       - |

There are no change to the test results as the instructions and tests were already implemented under CV32E40Pv1 and were not removed. This PR has instead updated these tests to match the specification in CV32E40Pv2.

[jeremybennett]

Reviewed and looks good to merge.