Builtin optimisation enhancement

openhwgroup / corev-gcc

GNU General Public License v2.0

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Builtin optimisation enhancement #22

Open MaryBennett opened 1 year ago

MaryBennett commented 1 year ago

The CORE-V builtins can be enhanced by expanding the rtl for each instruction. This would allow gcc to pattern match to these builtins. More testing with a simulator would be required.

Added, untested with simulator:

[x] XCVmac
[x] XCValu
[x] XCVelw
[x] XCVbi
[x] XCVmem
[x] XCVbitmanip
[ ] XCVsimd
[x] XCVhwlp

MaryBennett commented 8 months ago

This is required for upstreaming