Prevent non-xcvmem post-inc load/stores

[MaryBennett]

Issue [#64]

Files Changed:

• config/riscv/corev.md: Added support for soft/hardfloat normal and post-inc reg-reg load/stores.
• config/riscv/predicates.md: Added predicate to check if operand is non-immediate and non-post-inc.
• config/riscv/riscv.md: Likewise.
• config/riscv/riscv.cc: Clean up.
• testsuite/gcc.target/riscv/cv-mem-sw-compile-5.c: New test.

[MaryBennett]

Results for riscv.exp

Category	Previous	With commit	Delta
Expected passes	15400	15410	+10
Unexpected failures	85	85	-
Unexpected successes	-	-	-
Expected failures	6	6	-
Unresolved testcases	6	6	-
Unsupported tests	723	723	-

Results

Category	Previous	With commit	Delta
Expected passes	196017	196026	+9
Unexpected failures	19517	19517	-
Unexpected successes	2	2	-
Expected failures	839	839	-
Unresolved testcases	7	6	-1
Unsupported tests	4023	4023	-

Most unexpected failures are execution failures. There is currently no verilator model to test against.

Results for compile.exp

Category	Previous	With commit	Delta
Expected passes	14164	14164	-
Unexpected failures	-	-	-
Unexpected successes	-	-	-
Expected failures	-	-	-
Unresolved testcases	-	-	-
Unsupported tests	200	200	-

[jeremybennett]

Reviewed at the weekly call. Good to merge.