illegal operands `flw fa5,t2(s1) is generated from the latest release toolchain (05/Sep)

openhwgroup / corev-gcc

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illegal operands `flw fa5,t2(s1) is generated from the latest release toolchain (05/Sep) #73

Closed superflyers closed 1 year ago

superflyers commented 1 year ago

gcc_73.zip

MaryBennett commented 1 year ago

ARCH: rv32imfc_zicsr_zifencei_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0_xcvelw1p0 YES: flw rd, imm, (rs1) NO: flw rd, rimm. (rs1)

movSI_internal [5/9]

op1 is a mem (plus rimm rs1) => ADDRESS_REG

If predicate mem_plus_reg was true for op1, move_operand & movSI would be false.

There are no non-post-inc reg:reg load/store outside of CORE-V.

MaryBennett commented 1 year ago

Fixed in PR #75