openhwgroup / cv-hpdcache

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
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[Document Write Back] What are the events that writes data in the memory ? #35

Open khandelwaltanuj opened 2 weeks ago

khandelwaltanuj commented 2 weeks ago

Hi @cfuguet

Is it possible to give details of the events that causes a write acces to the memory ? As per my understand, when a dirty is evicted, ou a read/amo operation is performed on a dirty bit, it causes a write to memory.

Are there any other cases ?

Thanks a lot

Regards Tanuj

cfuguet commented 2 weeks ago

The cache initiates a write to the memory on any of the following conditions:

khandelwaltanuj commented 2 weeks ago

Thanks for your reply @cfuguet

So as I understand, a load operation with a write back on a dirty line does not causes a memory write operation.

Do you think, it would be nice to have this table in the documentations please ? Even if I know it may add a lot of verification work for me :O.

Regards, Tanuj

cfuguet commented 1 week ago

Hi @khandelwaltanuj,

Yes, a load hit with the write-back hint does not trigger a write when reading a dirty cacheline.

A load can only trigger a write in two scenarios:

  1. load, cache miss and the victim cacheline is dirty.
  2. load with the write-through hint, cache hit and the target cacheline is dirty.

César