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openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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Missing area metrics for ASIC synthesis #1002

Open thomasdingemanse opened 2 weeks ago

thomasdingemanse commented 2 weeks ago

Missing area metrics for ASIC synthesis

The FPGA synthesis section of the CV32E40P User Manual says the following about the area:

The core occupies an area of about XX kGE. With the FPU, the area increases to about XX kGE (XX kGE FPU, XX kGE additional register file).

It seems like XX is meant to be a placeholder for specific numbers. I'd be happy to help, but I'm not sure how the core should be synthesized for ASIC to get accurate area metrics. Is there an example workflow I could follow or a synthesis script I could use?

Component

Component:Doc

Steps to Reproduce

Not applicable.

pascalgouedo commented 2 weeks ago

Hi @thomasdingemanse , Yes ASIC synthesis section contains place-holders for CPU and FPU size numbers in KGE unit. All those sentences will be replaced by new text explaining the synthesis context and some new tables. We are collecting the numbers right now.

No workflow is available as the Core is available as a soft IP. An IOs constraint file is given as an example in constraints directory.