RTL Code Coverage Hole in cv32e40p_controller module line 399

openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest

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RTL Code Coverage Hole in cv32e40p_controller module line 399 #1004

Open pascalgouedo opened 2 weeks ago

pascalgouedo commented 2 weeks ago

Component

Component:RTL

Issue description

There are 2 conditions not covered on line 399 of cv32e40p_controller during all the simulation non-regressions. During FIRST_FETCH controller FSM state, there is test to check that interrupts during pending debug request or during debug is not taken. FIRST_FETCH is occurring 1 cycle after BOOT_SET or after SLEEP.

Was waived in v1 and has been waived in v2 as well.

399-1

399-2