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openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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RTL code coverage hole in CV32E40P lzc #1022

Open YoannPruvost opened 4 months ago

YoannPruvost commented 4 months ago

Component

Component:RTL

Issue Description

The interconnect between the core and the FPU has been designed to handle multiple cores to multiple FPU connections. As the verification has been done with a one-core setup, the LZC used to arbitrate between different core is under-utilized and some part of the code is unreachable in this setup.

As it was too late to implement a different solution in RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive those holes in v2.

MikeOpenHWGroup commented 3 months ago

Hi @YoannPruvost, can you provide some addition insight into this code coverage hole?