recipe for target 'testbench_verilator' failed (verilator Warning-COMBDLY) - when executing make in cv32e40p/sim/core/Makefile

Hello, I tried setting up the toolchain in a dockerfile (down below to reproduce the issue) like described in the Quickstart, but when executing the makefile I get the following error:

Compiling CORE TB and CV32E40P with Verilator
*******************************************************************************************
verilator --cc --sv --exe \
     \
    --Wno-lint --Wno-UNOPTFLAT \
    --Wno-MODDUP --top-module \
    tb_top_verilator /core_v_verif/cv32e40p/tb/core/tb_top_verilator.sv /core_v_verif/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv /core_v_verif/cv32e40p/tb/core/tb_riscv/riscv_rvalid_stall.sv /core_v_verif/cv32e40p/tb/core/tb_riscv/riscv_gnt_stall.sv /core_v_verif/cv32e40p/tb/core/mm_ram.sv /core_v_verif/cv32e40p/tb/core/dp_ram.sv \
    -f /core_v_verif/core-v-cores/cv32e40p/cv32e40p_manifest.flist \
    /core_v_verif/core-v-cores/cv32e40p/bhv/cv32e40p_core_log.sv \
    /core_v_verif/cv32e40p/tb/core/tb_top_verilator.cpp --Mdir cobj_dir \
    -CFLAGS "-std=gnu++11 -O2" \
    -Wno-BLKANDNBLK  

%Warning-COMBDLY: /core_v_verif/core-v-cores/cv32e40p/rtl/../bhv/cv32e40p_sim_clock_gate.sv:25:31: Non-blocking assignment '<=' in combinational logic process
                                                                                                  : ... This will be executed as a blocking assignment '='!
   25 |     if (clk_i == 1'b0) clk_en <= en_i | scan_cg_en_i;
      |                               ^~
                  ... For warning description see https://verilator.org/warn/COMBDLY?v=4.228
                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
                  *** See https://verilator.org/warn/COMBDLY before disabling this,
                  else you may end up with different sim results.
%Error: Exiting due to 1 warning(s)
Makefile:488: recipe for target 'testbench_verilator' failed
make[1]: Leaving directory '/core_v_verif/cv32e40p/sim/core'

When I add the --Wno-COMBDLY option to the verilator command

verilator --cc --sv --exe \
         \
        --Wno-lint --Wno-UNOPTFLAT --Wno-COMBDLY\
        --Wno-MODDUP --top-module \
        tb_top_verilator /core_v_verif/cv32e40p/tb/core/tb_top_verilator.sv /core_v_verif/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv /core_v_verif/cv32e40p/tb/core/tb_riscv/riscv_rvalid_stall.sv /core_v_verif/cv32e40p/tb/core/tb_riscv/riscv_gnt_stall.sv /core_v_verif/cv32e40p/tb/core/mm_ram.sv /core_v_verif/cv32e40p/tb/core/dp_ram.sv \
        -f /core_v_verif/core-v-cores/cv32e40p/cv32e40p_manifest.flist \
        /core_v_verif/core-v-cores/cv32e40p/bhv/cv32e40p_core_log.sv \
        /core_v_verif/cv32e40p/tb/core/tb_top_verilator.cpp --Mdir cobj_dir \
        -CFLAGS "-std=gnu++11 -O2" \
        -Wno-BLKANDNBLK

the verilator command is successful. Is this ok if I do it like this?

Then the makefile enters the simulation result dir _/core_v_verif/cv32e40p/sim/core/simulation_results/hello-world/0/testprogram/bsp Here the makefile won't find a header file

/opt/riscv32/bin/riscv32-unknown-linux-gnu-gcc -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic -c /core_v_verif/cv32e40p/bsp/syscalls.c -o syscalls.o
In file included from /opt/riscv32/sysroot/usr/include/features.h:497,
                 from /opt/riscv32/sysroot/usr/include/sys/stat.h:25,
                 from /core_v_verif/cv32e40p/bsp/syscalls.c:20:
/opt/riscv32/sysroot/usr/include/gnu/stubs.h:8:11: fatal error: gnu/stubs-ilp32.h: No such file or directory
    8 | # include <gnu/stubs-ilp32.h>
      |           ^~~~~~~~~~~~~~~~~~~

Is this the case because FROM pwn2de4d/riscv-toolchain:latest does not have installed the rv32imc riscv toolchain?

Here is the dockerfile to reproduce it, it takes roughly 20min on my computer to build

# Use existing RISCV toolchain image as the base
FROM pwn2de4d/riscv-toolchain:latest

# Set environment variables
ENV CORE_V_VERIF=/core_v_verif

ENV CV_SW_TOOLCHAIN=/opt/riscv32
ENV CV_SW_PREFIX=riscv32-unknown-linux-gnu-
ENV CV_SW_MARCH=rv32imc

# Install dependencies
RUN apt-get update && \
    apt-get install -y python3-pip git make build-essential wget libssl-dev nano && \
    rm -rf /var/lib/apt/lists/*

# Set environment variables
ENV PYTHON_VERSION=3.12.0
ENV PYTHON_SRC=/usr/src/python

# Create source directory for Python
RUN mkdir -p ${PYTHON_SRC}

# Download Python 3.12 source code
RUN wget https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tgz -O ${PYTHON_SRC}/Python-${PYTHON_VERSION}.tgz

# Extract the source code
RUN tar -xvf ${PYTHON_SRC}/Python-${PYTHON_VERSION}.tgz -C ${PYTHON_SRC}

# Compile and install Python 3.12
WORKDIR ${PYTHON_SRC}/Python-${PYTHON_VERSION}
RUN ./configure --enable-optimizations
RUN make -j4
RUN make altinstall

# Verify the installation
RUN python3.12 --version

# Set Python 3.12 as the default python3
RUN update-alternatives --install /usr/bin/python3 python3 /usr/local/bin/python3.12 1
RUN apt-get install ca-certificates

# Clone the core-v-verif repository
RUN git clone https://github.com/openhwgroup/core-v-verif.git $CORE_V_VERIF
RUN pip3 install -r $CORE_V_VERIF/bin/requirements.txt

# Clone and build verilator
RUN git clone https://github.com/verilator/verilator /verilator
WORKDIR /verilator
RUN git checkout v4.228
# RUN git checkout v5.028
RUN autoconf         # Create ./configure script
RUN ./configure      # Configure and create Makefile
RUN make -j 4  # Build Verilator itself (if error, try just 'make')
RUN make install

# Set RISCV toolchain in the PATH
ENV PATH=$CV_SW_TOOLCHAIN/bin:$PATH

# Navigate to the simulation directory and run make
WORKDIR $CORE_V_VERIF/cv32e40p/sim/core
RUN sed -i 's|--Wno-lint --Wno-UNOPTFLAT|--Wno-lint --Wno-UNOPTFLAT --Wno-COMBDLY|g' Makefile
RUN make

Also, is there any Dockerfile where the full and correct toolchain is already installed?

openhwgroup / cv32e40p

recipe for target 'testbench_verilator' failed (verilator Warning-COMBDLY) - when executing make in cv32e40p/sim/core/Makefile #1032