openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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Documentation Error Performance Counters #179

Closed Steinegger closed 4 years ago

Steinegger commented 5 years ago

In the doc/user_manual.doc on page 28 there's and error regarding the CSR addresses for the PCMR and PCER performance registers. As noted in the table on page 21 the the rtl/include/riscv_defines.sv file the addresses should be 0x7E instead of 0x7A.

https://github.com/pulp-platform/riscv/blob/3c3400b0e6681d3cf20d0463e3d9d1fa021296fc/rtl/include/riscv_defines.sv#L440-L446

Screenshot from 2019-10-03 16-06-15

Screenshot from 2019-10-03 16-04-49

davideschiavone commented 4 years ago

61593531b7cbb22549e3d18d704b509c450ec412