openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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MIE Field of MSTATUS CSR Is Updated Wrongly #182

Open shetalani opened 5 years ago

shetalani commented 5 years ago

RISC-V Specification:

Issue Description:

MIE field of MSTATUS CSR is not updated to take the value of MPIE when MRET instruction is executed and the MPP field has the value 0.

Example:

As shown below, the instruction 32'h30200073 (mret) is decoded at time point t##0 where the current privilege is M and MPP has the value associated with U mode. When it updates MSTATUS value at t##3, it sets all fields correctly except MIE, which stays asserted instead of taking the value of MPIE.

On the other hand, in the opposite scenario, when an exception occurring in U mode is handled, MPIE is not taking the value of MIE as the specification states.

Issue_15


Product: OneSpin 360 DV-Verify App: RVV Tool's version: 2019.2.2

silabs-PaulZ commented 4 years ago

Hi @shetalani , The User mode was removed when we ported RISCY to CV32E40P. We will add User Mode back in on the follow-on part, CV32E40. I hope to look at the user mode issues at a later date.

Regarding machine mode, I am now seeing the correct behavior. After mret instruction call, the following holds true:

image

image

MPRV, UIE, and UPIE are tied to 0 in CV32E40P.