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openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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Removing the PMP file from the RTL folder #640

Closed davideschiavone closed 3 years ago

davideschiavone commented 3 years ago

shall we remove the PMP file from the RTL folder?

if people look for it for older version of the core, we can still point to an old commit where the file is present.

The current RTL fails to be formatted by verible and it containts casex from systemverilog, which makes the life of some EDA tools hard.

In addition, as today, there is no plan to integrate the PMP into CV32E40P.

best Davide

Silabs-ArjanB commented 3 years ago

I would say 'yes', let's remove that file and any references to it.

MikeOpenHWGroup commented 3 years ago

Its my understanding that the reason this question came up is that cv32e40p_pmp.sv contains a casex statement. As far as I am aware, it is the only occurrence of a casex statement in any CORE-V RTL.

Just FYI, it is my understanding that the RTL coding style guidelines for CORE-V IP is essentially the lowRISC Ibex SystemVerilog coding style guide. Under wildcards-in-case-items, these guidelines state that casex statements should not be used.

davideschiavone commented 3 years ago

Not only that. Also the verible-format tool does not pass (the casex is also present in the tracer and verible was able to pass thought it). In addition, none is using that file anyway. It may create confusion to have a SV file in the RTL folder which is not used or instantiated anyway.

davideschiavone commented 3 years ago

close by #645