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openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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Missing files #945

Closed Amal-k-Ayyan closed 5 months ago

Amal-k-Ayyan commented 5 months ago

Following files where found missing: core_clock_gate gen_clock_gate cv32e40p_pmp cv32e40p_clock_gate

MikeOpenHWGroup commented 5 months ago

Hi @Amal-k-Ayyan, thanks for your interest in OpenHW cores. I am afraid I do not understand your comment. What are these files missing from? Please make sure you are using the most up to date version of the code. For example, as of #643, the file rtl/cv32e40p_pmp.sv not longer exists.

Amal-k-Ayyan commented 5 months ago

Hi @MikeOpenHWGroup I tried to get the schematic from rtl code given in the repo using vivado. But it gave errors showing above mentioned files where missing.

MikeOpenHWGroup commented 5 months ago

Please ensure you have read the Core Integration section of the User Manual, particularly the Parameters, Clock-gating and Synthesis Guidelines.

If you are still having trouble after that, please provide the exact command-lines you are using, start with git clone.... If there are any files you are using that are not part of this repo, please attach these to the issue.