openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
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FPU power consumption #965

Closed pascalgouedo closed 3 months ago

pascalgouedo commented 3 months ago

FPU has its own clock gating cell in cv32e40p_top which is only disabled when the Core is in sleep mode due to wfi instruction. More power consumption power saving could be done by enabling its clock only when an FPU instruction is really executed.

pascalgouedo commented 3 months ago

Corrected with PR #966