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openhwgroup / cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P
https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/
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Removed exceptions 4 and 6 from possible tdata2 entries. Added assert… #430

Closed silabs-oysteink closed 1 year ago

silabs-oysteink commented 1 year ago

…ion to check that exceptions 4 and 6 never happen.

silabs-oysteink commented 1 year ago

Should fix issue #429