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openhwgroup / cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P
https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/
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Fix for issue #116 #437

Closed silabs-oysteink closed 1 year ago

silabs-oysteink commented 1 year ago

Added shadowcopy to mcause for both CLIC and CLINT. Hooked up mcause_rd_error.

SEC clean.

silabs-oysteink commented 1 year ago

MASK for mcause will be introduced once PR #836 on E40X is merged over.