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openhwgroup / cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P
https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/
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Added usage of csr_next_value for cpuctrl and mstateen0. #441

Closed silabs-oysteink closed 1 year ago

silabs-oysteink commented 1 year ago

Changed shadowcopy parameter for mcause from '1' to 'SECURE'. Changed priv_lvl_mask from 32 bits to 2 bits.

SEC clean.